Attosecond Precision Photonic / Electronic Systems
The goal of our research activities is to leverage the low jitter properties of mode-locked lasers and the high resolution available at optical frequencies to achieve long-term sub-femtosecond/attosecond precision photonic or optoelectronic systems. These developments are most important in the areas of large-scale timing distribution and synchronization of next-generation accelerators and light sources and analog-to-digital conversion. Accurate conversion of wideband multi-GHz analog signals into the digital domain has long been a target of analog-to-digital converter (ADC) developers, driven by applications in radar systems, software radio, medical imaging, and communication systems. Aperture jitter has been a major bottleneck on the way towards higher speeds and better accuracy. Photonic ADCs, which perform sampling using ultra-stable optical pulse trains generated by mode-locked lasers, have been investigated for many years as a promising approach to overcome the jitter problem and bring ADC performance to new levels.
Purely electronic systems are currently limited to about 100 fs timing accuracy because of the jitter performance of integrated microwave oscillators used and intrinsic limitations in time resolution by the speed and stability of electronic components. Over the last years, we have demonstrated that the photonic approach can deliver on its promise by digitizing a 41 GHz signal with 7.0 effective bits using a photonic ADC built from discrete components. This accuracy corresponds to a timing jitter of 15 fs – a 4-5 times improvement over the performance of the best electronic ADCs which exist today. On the way towards an integrated photonic ADC, a silicon photonic chip with core photonic components was fabricated and used to digitize a 10 GHz signal with 3.5 effective bits.
Timing jitter in mode-locked lasers
The timing jitter of optical pulse trains from passively mode-locked solid-state lasers has been theoretically predicted to be below a femtosecond in the high frequency range. In each ultrashort optical pulse, a large number of photons are concentrated in an extremely short pulse (~100 fs or below), which makes it robust against perturbations in timing by noise photons. In the last few years, there has been a remarkable progress in high-repetition-rate and ultralow-noise mode-locked lasers, largely driven by the motivation for high-precision time/frequency control and measurement. Recently, our group has demonstrated ultra-low-jitter 200-MHz fiber lasers and solid-state lasers [1,2] and the scaling of its repetition rate to 3 GHz by using highly doped fibers  as well as a 400-MHz integrated Er-waveguide laser . The latter has a potential for CMOS-compatible integrated on-chip mode-locked lasers.
Photonic analog-to-digital conversion
The field of electronic data conversion has witnessed significant progress over the last decade. With the unity-gain frequency of CMOS technology reaching hundreds of gigahertz and matured SiGe technology, data converters based on the silicon platform operating at sampling rates of tens of GSa/s now exist. While radio frequency (RF) electronic data converters are now running at unprecedented sampling rates, their performance, as defined by effective number of bits (ENOB), has not improved commensurately. A major factor limiting the progress towards higher rates and resolutions is aperture jitter, i.e., inability of ADCs to sample at precisely defined times. Fig. 1 shows ENOB as a function of input frequency for high-performance electronic ADCs, as reviewed by Walden , including some ADCs that have appeared afterwards.
Dashed lines represent limits on ENOB due to jitter. The best electronic ADCs deliver jitter levels of 60-80 fs in the 100-400 MHz frequency range; reducing the jitter further becomes increasingly difficult, especially beyond gigahertz frequencies, and if the past is a good prediction for the future, it will take nearly a decade to improve the jitter performance by an order of magnitude. As discussed below, ultra-stable mode-locked laser sources with jitter levels many orders of magnitude lower exist today; if used for sampling, they could improve ADC performance by orders of magnitude.
In our work, the potential of the photonic approach is demonstrated by sampling a 41 GHz signal with record 7.0 ENOB with a discrete-component photonic ADC. This performance is equivalent to 15 fs jitter, a significant improvement over today’s state of the art. A practical photonic ADC must be integrated on a chip, which can be realized using rapidly developing silicon photonics technology. A chip incorporating the core components of the photonic ADC has been fabricated and shown to produce 3.5 ENOB for a 10 GHz input. These results indicate that fast and accurate photonic ADCs can be realized today and suggest that even better results can be achieved in the future through the synergistic integration of electronics, silicon photonics, and ultra-stable mode-locked laser technologies.
To overcome the aperture jitter in the sampling process, photonic ADCs perform sampling in the optical domain using low-jitter optical pulse trains. Sampling occurs when such pulse trains pass through an electro-optic modulator while the voltage signal to be sampled is applied; the output pulse energies represent the RF signal values at the temporal positions of the pulses. A major benefit of this approach is that the jitter of the optical sampling process is determined by the jitter of the optical pulse train, which, as explained above, can be extremely low. Another benefit is that electro-optical interactions are very fast; the aperture over which the RF signal is sampled, as defined by the duration of optical pulses, can be very short. Moreover, to handle the enormous data flow generated when sampling high-frequency signals, photonic approaches offer the possibility to split the input into multiple lower-rate channels to be processed in parallel, as described below.
The ADC architecture used in our work is illustrated in Fig. 2. In an N-channel ADC, an optical pulse train with repetition period T is split into N trains, each centered at a different wavelength, with a 1-to-N wavelength demultiplexer. These trains pass through optical delay lines, which introduce incremental delays of T/N between them. The trains are then recombined with a multiplexer to produce a pulse train with repetition period T/N, where pulse wavelengths repeat periodically every N pulses. This operation establishes a discrete time-to-wavelength mapping within the pulse train, i.e., pulses separated in time are also separated in wavelength [7,8]. A continuous version of time-to-wavelength mapping can be established with a dispersive fiber. The next step is the optical sampling, i.e., modulation of the optical pulse train with the RF signal to be sampled. The modulated pulse train is then taken apart into N channels using a wavelength demultiplexer matched to the one used earlier to establish the time-to-wavelength mapping. The pulse trains in all channels are converted to the electrical domain with photodetectors, boosted in amplitude with RF amplifiers, and digitized with electronic ADCs. These ADCs are synchronized with the mode-locked laser and take one sample per pulse, exactly at the pulse peak. Although the electronic ADCs have some aperture jitter, the accuracy of the photonic ADC is insensitive to it because the electronic ADCs sample the relatively flat-top region of the pulses. During post-processing, the samples captured in different channels are compensated for distortions and interleaved to obtain the final digital representation of the RF signal. Note that the scheme with N channels not only increases the sample rate by N, but also reduces the required analog bandwidth of photodetectors and electronic ADCs, which need to be only as high as several times the original laser repetition rate to avoid intersymbol interference between subsequent pulses. Importantly, because of reduced analog bandwidth at the input of electronic ADCs, the impact of comparator ambiguity – another major factor limiting accuracy at high frequencies – is completely eliminated.
Photonic ADCs have been actively investigated over the last decades; an overview and classification of photonic ADCs can be found in an excellent review by Valley .
Demonstration of a discrete-component photonic ADC
To demonstrate low-jitter sampling of high-frequency signals, a photonic ADC based on the concept described above (Fig. 2) was built using discrete commercially available components. This section describes the implementation of this photonic ADC with two 1.05 GSa/s channels interleaved to provide 2.1 GSa/s aggregate sampling rate, and presents results of digitization of a 41 GHz test signal.
The only custom-built component used in the experiments was the low-jitter mode-locked laser, which was a soliton mode-locked Er-doped fiber laser, self-starting with a semiconductor saturable Bragg reflector. The ADC was tested by digitizing a single-tone 41 GHz signal. Spectra of the data points captured in two channels are shown in Fig. 3(a); these spectra are the Fourier transforms of the raw unprocessed data, only with Blackman windowing function applied to improve the dynamic range.
Fig. 3(b) shows the final result – the spectrum of the 41 GHz RF signal sampled at 2.1 GSa/s with 7.0 ENOB and 52 dBc SFDR. This significantly exceeds any result achieved with electronic ADCs at such high frequencies (see Fig. 1). Such performance corresponds to the aperture jitter of 15 fs or smaller – a 4-5 times improvement over the jitter of the best electronic ADCs and about an order of magnitude improvement over electronic ADCs operating at frequencies above 10 GHz. As explained above, the laser jitter, already low in this experiment, can be orders of magnitude lower, opening the door to completely new ADC performance levels.
The photonic ADC discussed above was made with discrete components in a laboratory setting, similarly to most other photonic ADCs demonstrated to date. However, to be a viable alternative to electronic ADCs, a photonic ADC must be integrated on a chip. Integration enables robustness, miniaturization, potential low-cost mass production, and promises to improve power efficiency and signal integrity by eliminating interconnects between separate chips. A major benefit of the approach pursued in our work is that it allows integration, and a full photonic ADC can potentially be implemented on a single chip using silicon photonics technology, as envisaged in Fig. 4. Such an ADC would use microring-resonator filters, a silicon carrier-depletion modulator and germanium or silicon defect-based photodetectors. Post-detection electronics, electronic ADCs, and digital error correction circuits would be integrated on the same CMOS chip. The demultiplexer, time delays, and multiplexer necessary to create a wavelength-interleaved pulse train can also be on the same chip. The pulse train can be generated with a separate chip, for example with an integrated erbium-doped mode-locked planar waveguide laser . This ADC would be an example of a device operating on completely new principles enabled by silicon photonics and electronic-photonic integration.
In a move towards a fully-integrated photonic ADC, a chip with core components of the above ADC has been created. The chip included a modulator, two matched three-channel filter banks, and photodetectors; the packaged chip is shown in Fig. 5(a), and its top-view photograph is shown in Fig. 5(b). The chip was fabricated on a Unibond silicon wafer with 3 µm buried oxide layer using conventional 248 nm optical lithography at MIT Lincoln Laboratory.
The photonic ADC chip was used to sample a 10 GHz RF signal. The testbed was similar to the one used for the discrete component ADC demonstration, except now the heart of the ADC – the modulator, filters, and photodetectors – was on a single silicon chip, as described above. Two out of the available three wavelength channels were used, providing 2.1 GSa/s aggregate sampling rate. In this experiment the effective number of bits and spur-free dynamic range was limited to 3.5 ENOB and 39 dBc SFDR, respectively, mostly due to the low efficiency of the silicon defect detectors.
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